1. Field of the Invention
The present invention relates generally to a semiconductor memory device and a method of manufacturing the same, and more particularly to a buried plate type DRAM (dynamic random access memory) and a method of manufacturing the same.
2. Description of the Related Art
Recently, as the capacity of a semiconductor memory device such as a DRAM is increased year by year, various devices have been proposed to increase the integration density of a memory. A 1-transistor 1-capacitor cell structure is generally known as a memory cell for use in a DRAM. A 3-transistor cell and a 4-transistor cell are also known. The 1-transistor 1-capacitor cell is most suitable for high integration, since one memory cell is constituted by a small number of elements. Various types of DRAM having a 1-transistor 1-capacitor cell such as a planar type, stacked type and buried plate type are known as improved memories to obtain a large mount of memory capacity with a small capacitor. The buried plate type DRAM is disclosed in, for example, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 35, No. 8, August 1988, pp. 1257-1261, "Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring", Kaga et al.
A memory cell of a buried plate type DRAM is an example of arrangement in which a storage capacitance is formed three-dimensionally. In the memory cell, a deep trench is formed in a silicon substrate in a direction perpendicular to the main surface thereof and a memory capacitor is formed on the side wall of the trench. Therefore, the cell area can be smaller and the memory capacity can be greater as compared to the planar type DRAM. Further, in the planer type or stacked type DRAM, since a greater step is formed on the substrate surface as the cell area is smaller, a wiring layer formed on the substrate surface may be cut at the step. On the other hand, in the buried plate type DRAM, since the plate electrode of a capacitor is buried in the semiconductor substrate, the surface of a semiconductor body is flat and the patterning accuracy of a wiring layer is increased.
According to a conventional method of manufacturing a memory cell of the buried plate type DRAM, an impurity such as As or P is ion-injected into a bottom portion of a trench, and then the bottom portion is heated for a long period of time, to diffuse the injected impurity and connect plate diffusion regions of adjacent trenches. However, for this purpose, thermal diffusion for a long period of time and impurity injection with high energy are required. As a result, the heat may adversely affect the other active regions (impurity diffusion layers). To avoid the thermal influence, it is well known a method of forming a buried region serving as a plate diffusion region on a semiconductor substrate by epitaxial growth, instead of forming a plate diffusion region by diffusing an impurity through a bottom portion of a trench. However, this method lowers manufacturing yield of memory cells and requires high cost. In addition, since the area at which a plate diffusion region is in contact with a plate electrode is relatively small, an apparent plate resistance is increased and an operation margin is decreased.